The present invention relates generally to memory devices, and more particularly to a memory array datapath architecture .
Memory devices are integral to a computer system, and to many electronic circuits. Continuous improvements in the operating speed and computing power of a central processing unit (CPU) enable operation of an ever-greater variety of applications, many of which require faster and larger memories. Larger memories can be obtained by shrinking the geometry of the memory cells and data lines within the memory devices.
With the larger memory, the memory device typically includes many device input/output (I/O) pins to support the concurrent access of many data bits to and from the device. These I/O pins are interconnected to all memory cells within the memory device through a structure of interconnections (also referred to as a datapath structure). As the number of I/O pins increases and as the number of memory cells in the memory device grows, the datapath structure also grows in complexity.
The memory device is also typically designed to support multiple modes of operation, such as normal write, block write, and read operations. These various operating modes are necessary to provide the required functionality. In a normal write operation, M data bits from M device I/O pins are provided to M memory cells. In a block write operation, multiple data bits can be written to many memory cells. A particular bit in a block write can be written to one or more memory cells depending on the particular design of the memory device or the state of the control signals, or both. For a block write, the data bits are typically provided by a set of registers located within the memory device and the masking information is provided from the I/O pins. The masking information determines which ones of the memory cells are to be written. And in a read operation, M data bits from M memory cells are retrieved and provided to M device I/O pins.
The large number of device I/O pins and memory cells, together with the requirement to support multiple operating modes, typically result in a complex datapath structure. In fact, the design of a datapath structure that supports the various operating modes and provides the most interconnection flexibility is typically one of the most tedious task in the design of the memory device.
To support the various operating modes and to provide interconnection flexibility, additional internal data lines and multiplexers are typically provided in the datapath structure. The additional circuitry, while increasing flexibility, results in a larger circuit die area and increased cost. The increased die area is essentially a "die penalty" for the additional flexibility. Further, the additional circuitry compounds the complexity of the datapath structure, which often leads to a longer design cycle.
As can be seen, a datapath architecture that provides flexible interconnections and supports a wide variety of operating modes while incurring minimal die and cost penalties is highly desirable.